Saturday, June 30, 2012

How the world’s fastest supercomputer, Fujitsu’s K,

Fujitsu Kei



Fujitsu "K" supercomputer

Tired of cell phones and Mobile World Congress? Grab a bit of supercomputing news here. Fujitsu shared some details on how it managed to keep its K supercomputer running so efficiently at ISSCC last week. The K is currently the highest-performing supercomputer in the world, with a maximum speed of 10.5PFLOPS and a total of 705,024 cores. Such systems are notoriously power hungry; power consumption is one of the major hurdles DARPA identified in its recent call to US researchers to reinvent computing.
K improves efficiency by fine-tuning the power supply voltage of each and every CPU. According to the researchers, this type of customization was necessary to deal with the rise in CPU manufacturing variation; such variances can lead to significant differences in power consumption and operating temperature. As a result, researchers were able to reduce CPU power consumption by an average of 7W per chip.
Kei computer water-cooling
7W per core may not sound like much on a per-system basis, or even in a mid-sized server room. In the K’s case, such analysis knocked around one megawatt off the system’s total power consumption and reduced the annual operating cost by $1 million. The systems are also water cooled (water being substantially more efficient than air), which helps reduce costs and improve performance.
                                                                   
K supercomputer blade
Expect to see more of this type of optimization in the future — a lot more. The work the K team did in hand-tuning power supply voltages per physical CPU is exactly the sort of technique we expect to see adopted, potentially at every level. One of the issues plaguing semiconductor design teams is that as process nodes shrink, manufacturing variances become increasingly problematic; a tiny number of sub-optimal variances can lead to dramatically higher power consumption if they occur in the wrong places. This is one issue that Moore’s law-style transistor density actually exacerbates; the more transistors per die, the greater the chance of flaws in the manufacturing process.
While DARPA will undoubtedly be interested in applying these lessons to its own exascale computing initiative, we’d be surprised if mobile manufacturers weren’t taking their own notes. With transistor power consumption bottoming out as voltages approach minimum thresholds, power savings through optimizing other parts of the delivery system will be a prime target and a means of product differentiation.

No comments:

Post a Comment